Subthreshold Operation of SONOS Analog Memory to Enable Accurate Low-Power Neural Network Inference

Hardware accelerators that exploit analog in-memory computing offer an energy-efficient edge deployment solution for machine learning algorithms. We give an overview of the device requirements and hardware-software co-design principles for these systems to achieve efficient and accurate deep neural network (DNN) inference. We designed and fabricated a 40nm test chip with a 1024×1024 SONOS (siliconoxide-nitride-oxide-silicon) charge trapping memory array for DNN inference. Operating the SONOS memory in the subthreshold regime suppresses the effects of device variability on algorithm accuracy. We experimentally demonstrate accurate DNN inference using the test chip on CIFAR-100 image classification and project a chip-level efficiency of >50 TOPS/W for the SONOS inference accelerator, a 10× advantage over state-of-the-art digital inference accelerators.

@inproceedings{agrawal2022subthreshold,
  author    = {Vineet Agrawal and T. Patrick Xiao and Christopher H. Bennett and Ben Feinberg and Saurabh Shetty and Krishnaswamy Ramkumar and Harsha Medu and K. Thekkekara and Ramesh Chettuvetty and Samuel Leshner and Zharina Luzada and Long Hinh and Tuan Phan and Matthew J. Marinella and Sapan Agarwal},
  title     = {{Subthreshold Operation of SONOS Analog Memory to Enable Accurate Low-Power Neural Network Inference}},
  booktitle = {IEEE International Electron Devices Meeting (IEDM)},
  year      = {2022},
  month     = {dec},
  address   = {San Francisco, CA, USA},
  doi       = {10.1109/IEDM45625.2022.10019564}
}