Evaluation of HPC Workloads Running on Open-Source RISC-V Hardware

The emerging RISC-V ecosystem has the potential to improve the speed, fidelity, and quality of hardware/software co-design R &D activities. However, the suitability of the RISC-V ecosystem for co-design targeting HPC use cases is not yet well understood. In this paper, we examine the performance of several HPC benchmark workloads running on simulated open-source hardware RISC-V cores running under the FireSim FPGA-accelerated simulation tool. To provide a realistic and reproducible HPC software stack, we port the Spack package manager to RISC-V and use it to build our workloads. Our key finding is that each of the RISC-V cores evaluated is capable of running complex HPC workloads executing for long durations under simulation, with simulation rates of approximately 1/50th real-time. Additionally we provide a baseline set of performance results that can be compared against in future studies. Our results highlight the readiness of the RISC-V ecosystem for performing open co-design activities for HPC. We expect performance to improve as co-design activities targeting RISC-V ramp up and the RISC-V community makes further contributions to this space.

@inproceedings{bergervergiat2023riscv,
  author    = {Luc Berger-Vergiat and Suma Cardwell and Ben Feinberg and Simon Hammond and Clayton Hughes and Michael Levenhagen and Kevin Pedretti},
  title     = {{Evaluation of HPC Workloads Running on Open-Source RISC-V Hardware}},
  booktitle = {ISC High Performance 2023 Workshops},
  year      = {2023},
  month     = {may},
  address   = {Hamburg, Germany},
  doi       = {10.1007/978-3-031-40843-4_40}
}