Simulating Hybrid Analog + RISC-V Systems for HPC Applications

As digital scaling trends have slowed over the past decade, there has been renewed interest in new computing paradigms. Analog computing is one such alternative, and has the potential to provide performance and efficiency beyond what is achievable by digital systems, but many challenges remain. One important challenge is enabling complex applications to take advantage of analog components that only support a limited set of computational kernels. In this work, we examine one potential solution to this challenge, hybrid analog–digital systems in which analog accelerators function as tightly integrated coprocessors within each core. In this approach, the RISC-V ISA simplifies hybrid system design by providing a mature software stack for the digital components, enabling system designers to focus on the analog-specific aspects of the architecture and software. To investigate the viability of hybrid architectures for high-performance computing (HPC), we evaluate two iterative linear solvers on analog–digital RISC-V processors with the Structural Simulation Toolkit (SST). Our analysis shows that digital operations remain bottlenecks even in analog-dominated applications. This demonstrates the importance of further work on hybrid systems and on software to effectively balance analog and digital operations for large-scale applications.

@inproceedings{durbin2025simulating,
  author    = {Cameron Durbin and Jacob Flores and Thomas Weatherly and Ben Feinberg},
  title     = {{Simulating Hybrid Analog + RISC-V Systems for HPC Applications}},
  booktitle = {SC '25 Workshops},
  year      = {2025},
  month     = {nov},
  address   = {St. Louis, MO, USA},
  doi       = {10.1145/3731599.3767532}
}