Multiscale System Modeling of Single-Event-Induced Faults in Advanced Node Processors

Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor’s scope makes physically correct modeling computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level effects at a system scope, we present a multiscale simulation framework. Charge collection at the 1) device level determines 2) circuit-level transient duration and state-upset likelihood. Circuit effects, in turn, impact 3) register-transfer-level architecture-state corruption visible at 4) the system level. Thus, the physically accurate effects of SEEs in large-scale systems, executed on a high-performance computing (HPC) simulator, could be used to drive cross-layer radiation hardening by design. We demonstrate the capabilities of this model with two case studies. First, we determine a D flip-flop’s sensitivity at the transistor level on 14-nm FinFet technology, validating the model against published cross sections. Second, we track and estimate faults in a microprocessor without interlocked pipelined stages (MIPS) processor for Adams 90% worst case environment in an isotropic space environment.

@article{cannon2021multiscale,
  author    = {Matthew Cannon and Arun F. Rodrigues and Dolores Black and Jeff Black and Luis Bustamante and Matthew Breeding and Ben Feinberg and Michael Skoufis and Heather Quinn and Lawrence T. Clark and John S. Brunhaver and Hugh Barnaby and Michael McLain and Sapan Agarwal and Matthew J. Marinella},
  title     = {{Multiscale System Modeling of Single-Event-Induced Faults in Advanced Node Processors}},
  journal   = {IEEE Transactions on Nuclear Science},
  year      = {2021},
  volume    = {68},
  number    = {5},
  pages     = {980--990},
  doi       = {10.1109/TNS.2021.3071653}
}