ERSFQ Memory Controller


A memory controller system has been designed and implemented in ERSFQ technology at Hypres, Inc. Its microarchitecture and logic design are developed by the University of Rochester. The controller enables system simulation at an abstracted level while referencing the memory controller component as synthesized ERSFQ netlist. Its architecture is flexible enabling it to be scaled down to a minimal implementation which can be fabricated in Hypres’ existing capabilities. This scaled down version still contains the full feature set and identical architecture of the base design where only the FIFO depths and word widths have shrunk. It is more than just a single memory, data path or small block of logic. It includes virtually all the components and features found in today’s ASIC systems making it an ideal test case to develop superconducting designs and tool flows.

Implementation of such a system was challenging given the immaturity and mostly non-existence of EDA tools. To overcome this, a complete custom approach was initially explored. Over the course of the design project several steps were scripted and automated. This included pseudo-manual synthesis, clock/reset phasing, static timing analysis (STA), cell library and test bench development, etc. Verification at the circuit and logic levels was achieved with a single Verilog test bench and a common set of vectors. This single verification platform ensures functional equivalence between the ERSFQ Spice circuit and its corresponding Verilog logic netlist. The Verilog logic test bench includes all timing checks, runs fast and the model can be incorporated in higher level abstracted system simulations.

In Applied Superconductivity Conference (ASC) 2018